1. Field
Various embodiments of the present invention relate to a one-time programmable memory and, more particularly, to a technology for restoring data that is erroneously written in a one-time programmable memory, to an original state.
2. Description of the Related Art
Programming a laser fuse is accomplished by cutting the laser fuse with a laser. Generally, this means that laser fuses are programmable only in a wafer state and are unable to be programmed after the wafer is packaged.
An electrical fuse (hereinafter, referred to as an e-fuse) is used to overcome the limitations of the laser fuse. E-fuses use transistors that store data by changing the resistance between the gate and the drain/source thereof.
FIG. 1 is a diagram illustrating an e-fuse formed of a transistor operating as a resistor or a capacitor.
Referring to FIG. 1, the e-fuse includes a transistor T having a gate G and a drain/source D/S to which a ground voltage is applied.
When a power source voltage, which is tolerable to the transistor T, is applied to the gate G, the e-fuse operates as a capacitor C. Thus, there is no current flowing between the gate G and the drain/source D/S. However, when a high voltage, which is intolerable to the transistor T, is applied to the gate G, a gate oxide of the transistor T is broken down to short the gate G and the drain/source D/S, and thus the e-fuse operates as a resistor R. Accordingly, current flows between the gate G and the drain/source D/S of the e-fuse. The data of the e-fuse is recognized from the resistance value between the gate G and the drain/source D/S. To recognize the data of the e-fuse, two methods are used. First, the data of the e-fuse may be recognized directly without performing an additional sensing operation by increasing the size of the transistor T. Second, the data of the e-fuse may be recognized by sensing a current flowing through the transistor T using an amplifier. However, these two methods are disadvantageous in terms of circuit area because the transistor T of the e-fuse is designed to be large in size or an additional amplifier needs to be provided for each e-fuse.
As disclosed in U.S. Pat. No. 7,269,047, research is being carried out on a method for reducing the circuit area occupied by e-fuses.
FIG. 2 is a diagram illustrating a cell array 200 including e-fuses.
Referring to FIG. 2, the cell array 200 includes one-time programmable memory cells 201 to 216 arranged in N rows and M columns. The memory cells 201 to 216 include memory elements M1 to M16 and switching elements S1 to S16, respectively. For example, a memory cell 201 includes a memory element M1 and a switching element S1. The memory elements M1 to M16 are e-fuses having characteristics of a resistor or a capacitor based on whether they are ruptured. In other words, the e-fuses M1 to M16 may be regarded as resistive memory elements that store data according to the amount of resistance. The switching elements S1 to S16 electrically connect the memory elements M1 to M16 to column lines BL1 to BLM, respectively, under the control of row lines WLR1 to WLRN.
Hereafter, it is assumed that a second row and an Mt column are selected. In other words, it is assumed that a memory cell 208 is selected. Voltages applied to the selected memory cell 208 and unselected memory cells 201 to 207 and 209 to 216 during a program and read operation are described below.
Program Operation
The row line WLR2 of the selected row is activated and the other row lines WLR1 and WLR3 to WLRN are deactivated. Thus, the switching elements S5 to S8 are turned on, and the switching elements S1 to S4 and S9 to S16 are turned off. A high voltage that may break a gate oxide of the e-fuse, which is generally obtained by a charge pumping method using a power source voltage, is applied to a program/read line WLP2 of the selected row, and a low level voltage, e.g., a ground voltage, is applied to the other program/read lines WLP1 and WLP3 to WLPN. The selected column line BLM is coupled with a data access circuit (not shown), and the unselected column lines BLM1 to BLM−1 float. When inputted data is program data (e.g., ‘1’), the data access circuit drives the selected column line BLM to a logic low level and allows the memory element M8 of the selected memory cell 208 to be programmed (or ruptured). When the inputted data is not program data (e.g., ‘0’), the data access circuit drives the selected column line BLM to a logic high level and substantially prevents the memory element M8 of the selected memory cell 208 from being programmed. Since the unselected column lines BLM1 to BLM−1 float, the memory elements M5 to M7 are not programmed even though a high voltage is applied to the gates thereof.
Read Operation
The row line WLR2 of the selected row is activated and the other row lines WLR1 and WLR3 to WLRN are deactivated. Thus, the switching elements S5 to S8 are turned on, and the switching elements S1 to S4 and S9 to S16 are turned off. A voltage, which is appropriate for the read operation, e.g., a power source voltage, is applied to the program/read line WLP2 of the selected row, and a low level voltage, e.g., a ground voltage, is applied to the other program/read lines WLP1 and WLP3 to WLPN. The selected column line BLM is coupled with the data access circuit and the unselected column lines BLM1 to BLM−1 float. When current flows through the selected column line BLM, the data access circuit recognizes that the program element M8 is programmed. In other words, the data access circuit may recognize that the data of the memory cell 208 is ‘1’. When no current flows through the selected column line BLM, the data access circuit recognizes that the program element M8 is not programmed. In other words, the data access circuit may recognize that the data of the memory cell 208 is ‘0’.
Although it is illustrated herein that one column line BLM is selected among the column lines BL1 to BLM, several column lines may be selected at once. In other words, several memory cells belonging to one row may be simultaneously programmed or read.
FIG. 3 is a block diagram illustrating an e-fuse array circuit including the cell array 200 shown in FIG. 2.
Referring to FIG. 3, the e-fuse array circuit includes the cell array 200 shown in FIG. 2, a row circuit 310, a column decoder 320, and a data access circuit 330.
The row circuit 310 controls the row lines WLR1 to WLRN and the program/read lines WLP1 to WLPN and allows the program operation or the read operation to be performed as described above. A row address ROW_ADD inputted to the row circuit 310 designates a row selected from a plurality of rows, and a program/read signal PGM/RD inputted to the row circuit 310 directs the program operation or the read operation.
The column decoder 320 electrically connects a column line, which is selected from the column lines BL1 to BLM based on a column address COL_ADD, to the data access circuit 330. Hereafter, it is assumed that four column lines are simultaneous selected from the column lines BL1 to BLM.
The data access circuit 330 performs data access operations on the column lines selected by the column decoder 320. The data access circuit 330 controls the selected column line to be programmed/non-programmed based on input data DI<0:3> during the program operation. The data access circuit 330 detects whether current flows through the selected column lines and outputs the detected result as output data DO<0:4> during the read operation.
In a memory such as an e-fuse array circuit, when data is programmed once, the memory may not return to its previous state. In other words, the memory cells of an e-fuse array cannot generally be programmed again. Thus, a memory such as an e-fuse array circuit, in which data is programmable only once, is referred to as a one-time programmable memory. Therefore, a technology that may restore data, which is erroneously programmed in a one-time programmable memory, to an original state is in demand.